After a microelectronic chip or die has been manufactured, it is typically packaged before it is sold. The package provides electrical connection to the chip's internal circuitry, protection from the external environment, and heat dissipation. In one package system, a chip is “flip-chip” connected to a package substrate. In a flip-chip package, electrical leads on the die are distributed on its active surface and the active surface is electrically connected to corresponding leads on a package substrate.
FIGS. 1 through 3 illustrate a prior art method for flip-chip packaging a microelectronic chip or die. In FIG. 1, a portion of a microelectronic die 100 including a conductive bump 140 is illustrated. Microelectronic die 100 includes a substrate 105, a device layer 110, an interconnect region 115, and a land 120. Device layer 110 typically includes a variety of electrical circuit elements, such as transistors, conductors, and resistors, formed in and on a semiconductor substrate material. Interconnect region 115 includes layers of interconnected metal vias and metal lines, which are separated by dielectric materials, that provide electrical connection between the devices of device layer 110 and electrical routing to conductive lands, including land 120. Typically, a dielectric layer 125, a barrier metal 135 and a bump 140 are formed over land 120, with bump 140 providing a structure for electrical connection from die 100 to an external package substrate.
As shown in FIGS. 2 and 3, in a common flip-chip package system, microelectronic die 100 is turned over, or flipped, and bonded to a package substrate 150 such that its active surface, including bumps 140, faces a surface of package substrate 150. Bumps 140 are in alignment with solder bumps or balls 155 on the surface of package substrate 150, and electrical connections are formed between bumps 140 and balls 155 at joints 160. As shown, joints 160 typically include portions of bumps 140 being depressed into the solder bumps. Also illustrated in FIG. 3 is an underfill material 170 that is provided between die 100 and package substrate 150.
In some processes, the bumps 140 are copper. In such systems, the joints 160 may develop voids between bumps 140 and the solder balls 155. The growth of these voids, due to electromigration of copper can lead to many problems. For example, it may cause an increase in electrical resistance, leading potentially to broken interconnects and device failure.